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Minneapolis, MN... The SMTA, in conjunction with Chip Scale Review magazine,
announces plans for the Second Annual International Wafer-Level Packaging
Congress and Exhibition (IWLPC) to be held November 3-4 at the Doubletree
Hotel in San Jose, CA.
The IWLPC will track leading-edge IC packaging and test technologies with
special emphasis on 3D stacked packaging. The dual-track program will
address package design concerns, package assembly, fabrication technologies,
board design for chip scale packages, and test/reliability.
The conference will cover topics within two tracks on Wafer-Level Packaging
(WLP) and 3D Stacked Packaging / Chip Scale Packaging. The complete call
for papers can be found on the IWLPC event Web site on smta.org.
http://www.smta.org/iwlpc/call_for_papers.cfm
Abstracts of 200 words should be submitted there directly on-line or sent by
email no later than April 1 to SMTA director of education Kristin
Nafstad: kristin@smta.org.
The congress co-chairs are Dr. Ken Gilleo of ET-Trends LLC and Dr. Luu
Nguyen of National Semiconductor. The event includes a two-day technical
program and two days of exhibits, showcasing leading suppliers to the
semiconductor packaging and testing industry.
Visit the IWLPC event Web site on smta.org for developing information, and
contact Kristin Nafstad with any questions: 952-920-7682.
The SMTA membership is a network of professionals who build skills, share
practical experience and develop solutions in electronic assembly
technologies and related business operations.
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摘自SMTA网<|||>
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2005-1-27 |
